R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 473

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

TDRE
TEND
FER/ERS
Note that the TEND flag is set in different timings depending on the GM bit setting in SMR.
Figure 12.27 shows the TEND flag set timing.
I/O data
TXI
(TEND interrupt)
GM = 0
GM = 1
[Legend]
Ds:
D0 to D7: Data bits
Dp:
DE:
Ds
Transfer from TDR to TSR
Figure 12.26 Data Re-Transfer Operation in SCI Transmission Mode
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Figure 12.27 TEND Flag Set Timing during Transmission
Start bit
Parity bit
Error signal
nth transfer frame
Ds
D0
D1
[1]
D2
[2]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
D3
Transfer from TDR to TSR
12.5 etu
11.0 etu
D4
Retransfer frame
D5
Section 12 Serial Communication Interface (SCI)
D6
Rev. 3.00 Mar. 14, 2006 Page 435 of 804
D7
Dp
(DE)
[3]
[4]
Guard time
DE
Ds D0 D1 D2 D3 D4
Transfer from TDR to TSR
transfer frame
REJ09B0104-0300
(n + 1) th