R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 167

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
6.5
6.5.1
The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space and
register space for the on-chip peripheral modules. The number of cycles necessary for access
differs according the space.
Table 6.2 shows the number of access cycles for each on-chip memory space.
Table 6.2
In access to the registers for on-chip peripheral modules, the number of access cycles differs
according to the register to be accessed. When the dividing ratio of the operating clock of a bus
master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0
to n-1 are inserted for register access.
Table 6.3
Access Space
On-chip ROM space
On-chip RAM space
Module to be Accessed
DMAC registers
MCU operating mode, clock pulse
generator, power-down control, interrupt
controller, and bus controller registers
I/O port PFCR registers and WDT registers 2Pφ
TPU, PPG, SCI, and A/D registers and I/O
port registers other than PFCR
HCAN registers
SSU registers
Internal Bus
Access to Internal Address Space
Number of Access Cycles for On-Chip Memory Spaces
Number of Access Cycles for Registers of On-Chip Peripheral Modules
Access
Read
Read
Write
Read
2Iφ
Number of Cycles
4Pφ
2Pφ
3Pφ
2Iφ
Write
3Iφ
3Pφ
Rev. 3.00 Mar. 14, 2006 Page 129 of 804
One Iφ cycle
One Iφ cycle
Two Iφ cycles
Number of Access Cycles
Write Data Buffer Function
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Section 6 Bus Controller (BSC)
REJ09B0104-0300

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