R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 394

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 Programmable Pulse Generator (PPG)
10.4
Figure 10.2 shows a schematic diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in NDER are set to 1. An initial output value is determined by its
corresponding PODR initial setting. When the compare match event specified by PCR occurs, the
corresponding NDR bit contents are transferred to PODR to update the output values. Sequential
output of data of up to eight bits is possible by writing new output data to NDR before the next
compare match.
10.4.1
If pulse output is enabled, the NDR contents are transferred to PODR and output when the
specified compare match event occurs. Figure 10.3 shows the timing of these operations for the
case of normal output in groups 2 and 3, triggered by compare match A.
Rev. 3.00 Mar. 14, 2006 Page 356 of 804
REJ09B0104-0300
Operation
Output Timing
Figure 10.3 Timing of Transfer and Output of NDR Contents (Example)
Pulse output pin
P
TCNT
NDRH
TGRA
PODRH
PO8 to PO15
Compare match
A signal
Figure 10.2 Schematic Diagram of PPG
Normal output/inverted output
m
N
m
NDER
Q
Q
PODR
Output trigger signal
C
N
D
n
N + 1
Q
NDR
D
n
n
Internal data bus