R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 822

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 3.00 Mar. 14, 2006 Page 784 of 804
REJ09B0104-0300
Item
5.8.6 Interrupt Flags of Peripheral
Modules
6.6.1 Write Data Buffer Function
for Peripheral Module
Section 7 DMA Controller (DMAC)
7.2.6 DMA Mode Control Register
(DMDR)
•
7.4.2 Transfer Modes
(1) Normal Transfer Mode
(2) Repeat Transfer Mode
Bit 5
Page Revision (See Manual for Details)
124
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149
162
163
Amended
To clear an interrupt request flag of a peripheral
module by the CPU, the flag must be read from after
being cleared within the interrupt handling routine even
if the peripheral module clock is not generated by
dividing the system clock. This makes the request
signal synchronized with the system clock.
6.6.1 Write Data Buffer Function for Peripheral Module
This LSI has a write data buffer function for the
peripheral module.
…, if a peripheral module write continues for two cycles
or longer, and there is an internal access next, only the
peripheral module write is executed in the first two
cycles.
Amended
Data Transfer Acknowledge
This bit is valid while the DMA transfer is performed by
the on-chip module interrupt. This bit decides whether
the source flag selected by DMRSR is cleared or not.
0: The source flag is not cleared while the DMA transfer
1: The source flag is cleared while the DMA transfer is
Deleted
The TEND signal is output only in the last DMA
transfer. The DACK signal is output every time a
transfer request is received and a transfer starts.
Amended
The TEND and DACK signals are is output only in the
last DMA
performed by the on-chip module interrupt. Since the
source flag is cleared by the DMA transfer, there is
no need to request an interrupt to the CPU.
is performed by the on-chip module interrupt. Since
the source flag is not cleared by the DMA transfer, it
should be cleared by the CPU.