R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 354
R5F61525
Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5F61525.pdf
(846 pages)
- Current page: 354 of 846
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Section 9 16-Bit Timer Pulse Unit (TPU)
Figure 9.23 shows an example of PWM mode 2 operation.
In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare
match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the
output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase
PWM waveform.
In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as
the duty cycle.
Rev. 3.00 Mar. 14, 2006 Page 316 of 804
REJ09B0104-0300
TGRB_1
TGRA_1
TGRD_0
TGRC_0
TGRB_0
TGRA_0
H'0000
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TGRA
TGRB
H'0000
TIOCA
TCNT value
TCNT value
Figure 9.22 Example of PWM Mode Operation (1)
Figure 9.23 Example of PWM Mode Operation (2)
Counter cleared by
TGRA compare match
Counter cleared by
TGRB_1 compare match
Time
Time
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