R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 374

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 16-Bit Timer Pulse Unit (TPU)
(4)
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is
activated, the flag is cleared automatically. Figure 9.43 shows the timing for status flag clearing by
the CPU, and figure 9.44 shows the timing for status flag clearing by the DMAC.
The status flag and interrupt request signal are cleared in synchronization with Pφ after the DMAC
transfer has started, as shown in figure 9.44. If conflict occurs for clearing the status flag and
interrupt request signal due to activation of multiple DMAC transfers, it will take up to five clock
cycles (Pφ) for clearing them, as shown in figure 9.45. The next transfer request is masked for a
longer period of either a period until the current transfer ends or a period for five clock cycles (Pφ)
from the beginning of the transfer.
Rev. 3.00 Mar. 14, 2006 Page 336 of 804
REJ09B0104-0300
Status Flag Clearing Timing
P
Address
Status flag
Interrupt request
signal
Figure 9.44 Timing for Status Flag Clearing by DMAC Activation (1)
P
Address
Write
Status flag
Interrupt request
signal
Period in which the next transfer request is masked
Figure 9.43 Timing for Status Flag Clearing by CPU
T1
DMAC
read cycle
address
Source
TSR write cycle
T2
TSR address
T1
T1
Destination
T2
DMAC
write cycle
address
T2