R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 201

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(2)
In repeat transfer mode, one data access size of data is transferred at a single transfer request. Up
to 4 Gbytes can be specified as a total transfer size by DTCR. The repeat size can be specified in
DBSR up to 65536 × data access size.
The repeat area can be specified for the source or destination address side by bits ARS1 and ARS0
in DACR. The address specified as the repeat area returns to the transfer start address when the
repeat size of transfers is completed. This operation is repeated until the total transfer size
specified in DTCR is completed. When H'00000000 is specified in DTCR, it is regarded as the
free running mode and repeat transfer is continued until the DTE bit in DMDR is cleared to 0.
In addition, a DMA transfer can be stopped and a repeat size end interrupt can be requested to the
CPU when the repeat size of transfers is completed. When the next transfer is requested after
completion of a 1-repeat size data transfer while the RPTIE bit is set to 1, the DTE bit in DMDR is
cleared to 0 and the ESIF bit in DMDR is set to 1 to complete the transfer. At this time, an
interrupt is requested to the CPU when the ESIE bit in DMDR is set to 1.
The timing of the TEND signal is the same as in normal transfer mode.
Figure 7.9 shows the operation in repeat transfer mode while dual address mode is set.
When the repeat area is specified as neither source nor destination address side, the operation is
the same as the normal transfer mode operation shown in figure 7.8. In this case, a repeat size end
interrupt can also be requested to the CPU when the repeat size of transfers is completed.
Address B
Address T
Repeat Transfer Mode
A
A
Operation when the repeat area is specified
to the source side
Figure 7.9 Operations in Repeat Transfer Mode
Repeat size =
BKSZH
data access size
Transfer
Rev. 3.00 Mar. 14, 2006 Page 163 of 804
Section 7 DMA Controller (DMAC)
Address T
Address B
B
B
REJ09B0104-0300
Total transfer
size (DTCR)