R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 578

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 14 Synchronous Serial Communication Unit (SSU)
(2)
Figure 14.13 shows an example of transmission operation, and figure 14.14 shows a flowchart
example of data transmission. When transmitting data in clock synchronous communication mode,
the SSU operates as shown below.
In master mode, the SSU outputs a transfer clock and data. In slave mode, when a transfer clock is
input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock.
Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and
the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and
starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated.
When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to
SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been
transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time,
if the TEIE bit is set to 1, a TEI interrupt is generated.
While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit
is cleared to 0.
Rev. 3.00 Mar. 14, 2006 Page 540 of 804
REJ09B0104-0300
SSCK
SSO
TDRE
TEND
LSI operation
User operation
Data Transmission
Data written
to SSTDR
TXI interrupt
generated
Figure 14.13 Example of Transmission Operation
Bit 0
(Clock Synchronous Communication Mode)
Data written
to SSTDR
Bit 1
1 frame
Bit 7
TXI interrupt
generated
Bit 0
Bit 1
1 frame
Bit 7
TEI interrupt
generated