R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 508

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Controller Area Network (HCAN)
13.3.12 Mailbox Interrupt Mask Register (MBIMR)
MBIMR enables or disables interrupt requests by individual mailboxes.
Rev. 3.00 Mar. 14, 2006 Page 470 of 804
REJ09B0104-0300
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
MBIMR7
MBIMR6
MBIMR5
MBIMR4
MBIMR3
MBIMR2
MBIMR1
MBIMR0
MBIMR15
MBIMR14
MBIMR13
MBIMR12
MBIMR11
MBIMR10
MBIMR9
MBIMR8
MBIMR15
MBIMR7
R/W
R/W
15
1
7
1
MBIMR14
Initial
Value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MBIMR6
R/W
R/W
14
1
6
1
MBIMR13
MBIMR5
R/W
R/W
13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
5
1
MBIMR12
MBIMR4
Description
Mailbox Interrupt Mask (MBIMRx)
When MBIMRn (n = 1 to 15) is cleared to 0, the
interrupt request in mailbox n is enabled. When
set to 1, the interrupt request is masked.
The interrupt source in a transmit mailbox is TXPR
clearing caused by transmission end or
transmission cancellation. The interrupt source in
a receive mailbox is RXPR setting on reception
end.
R/W
R/W
12
1
4
1
MBIMR11
MBIMR3
R/W
R/W
11
1
3
1
MBIMR10
MBIMR2
R/W
R/W
10
1
2
1
MBIMR1
MBIMR9
R/W
R/W
9
1
1
1
MBIMR0
MBIMR8
R/W
R/W
8
1
0
1