R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 85

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Table 2.7
Instruction
LDMAC
STMAC
Instruction
AND
OR
XOR
NOT
Logic Operation Instructions
Size
Size
B/W/L
B/W/L
B/W/L
B/W/L
Function
Rs → MAC
Loads data from a general register to MAC.
MAC → Rd
Stores data from MAC to a general register.
Function
(EAd) ∧ #IMM → (EAd), (EAd) ∧ (EAs) → (EAd)
Performs a logical AND operation on data between immediate data,
general registers, and memory.
(EAd) ∨ #IMM → (EAd), (EAd) ∨ (EAs) → (EAd)
Performs a logical OR operation on data between immediate data,
general registers, and memory.
(EAd) ⊕ #IMM → (EAd), (EAd) ⊕ (EAs) → (EAd)
Performs a logical exclusive OR operation on data between immediate
data, general registers, and memory.
∼ (EAd) → (EAd)
Takes the one's complement of the contents of a general register or a
memory location.
Rev. 3.00 Mar. 14, 2006 Page 47 of 804
REJ09B0104-0300
Section 2 CPU

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