R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 14

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.4
9.5
9.6
9.7
9.8
9.9
Section 10 Programmable Pulse Generator (PPG)............................................ 345
10.1 Features.............................................................................................................................. 345
10.2 Input/Output Pins............................................................................................................... 346
Rev. 3.00 Mar. 14, 2006 Page xiv of xxxviii
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
Operation ........................................................................................................................... 299
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
Interrupt Sources................................................................................................................ 326
DMAC Activation.............................................................................................................. 329
A/D Converter Activation.................................................................................................. 329
Operation Timing............................................................................................................... 330
9.8.1
9.8.2
Usage Notes ....................................................................................................................... 337
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.9.6
9.9.7
9.9.8
9.9.9
9.9.10 Conflict between Buffer Register Write and Input Capture.................................. 341
9.9.11 Conflict between Overflow/Underflow and Counter Clearing ............................. 342
9.9.12 Conflict between TCNT Write and Overflow/Underflow .................................... 342
9.9.13 Multiplexing of I/O Pins ....................................................................................... 343
9.9.14 Interrupts and Module Stop Mode ........................................................................ 343
Timer Mode Register (TMDR)............................................................................. 270
Timer I/O Control Register (TIOR)...................................................................... 272
Timer Interrupt Enable Register (TIER)............................................................... 290
Timer Status Register (TSR)................................................................................. 292
Timer Counter (TCNT)......................................................................................... 296
Timer General Register (TGR) ............................................................................. 296
Timer Start Register (TSTR) ................................................................................ 297
Timer Synchronous Register (TSYR)................................................................... 298
Basic Functions..................................................................................................... 299
Synchronous Operation......................................................................................... 305
Buffer Operation................................................................................................... 307
Cascaded Operation .............................................................................................. 311
PWM Modes......................................................................................................... 313
Phase Counting Mode........................................................................................... 318
Input/Output Timing............................................................................................. 330
Interrupt Signal Timing ........................................................................................ 334
Module Stop Mode Setting ................................................................................... 337
Input Clock Restrictions ....................................................................................... 337
Caution on Cycle Setting ...................................................................................... 338
Conflict between TCNT Write and Clear Operations........................................... 338
Conflict between TCNT Write and Increment Operations ................................... 339
Conflict between TGR Write and Compare Match............................................... 339
Conflict between Buffer Register Write and Compare Match.............................. 340
Conflict between TGR Read and Input Capture ................................................... 340
Conflict between TGR Write and Input Capture .................................................. 341