R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 90

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 2 CPU
Table 2.11 System Control Instructions
Rev. 3.00 Mar. 14, 2006 Page 52 of 804
REJ09B0104-0300
Instruction
TRAPA
RTE
RTE/L
SLEEP
LDC
STC
ANDC
ORC
XORC
NOP
Size
B/W
L
B/W
L
B
B
B
Starts trap-instruction exception handling.
Returns from an exception-handling routine.
Returns from an exception-handling routine, restoring data from the stack
to multiple general registers.
Causes a transition to a power-down state.
#IMM → CCR, (EAs) → CCR, #IMM → EXR, (EAs) → EXR
Loads immediate data or the contents of a general register or a memory
location to CCR or EXR.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.
Rs → VBR, Rs → SBR
Transfers the general register contents to VBR or SBR.
CCR → (EAd), EXR → (EAd)
Transfers the contents of CCR or EXR to a general register or memory.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.
VBR → Rd, SBR → Rd
Transfers the contents of VBR or SBR to a general register.
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with immediate data.
PC + 2 → PC
Only increments the program counter.
Function

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