R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 468

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 12 Serial Communication Interface (SCI)
12.7.2
Figure 12.22 shows the data transfer formats in smart card interface mode.
• One frame contains 8-bit data and a parity bit in asynchronous mode.
• During transmission, at least 2 etu (elementary time unit: time required for transferring one bit)
• If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu
• If an error signal is sampled during transmission, the same data is automatically re-transmitted
For communication with the IC cards of the direct convention and inverse convention types,
follow the procedure below.
Rev. 3.00 Mar. 14, 2006 Page 430 of 804
REJ09B0104-0300
is secured as a guard time after the end of the parity bit before the start of the next frame.
has passed from the start bit.
after at least 2 etu.
[Legend]
Ds:
D0 to D7: Data bits
In normal transmission/reception
When a parity error is generated
Data Format (Except in Block Transfer Mode)
Figure 12.22 Data Formats in Normal Smart Card Interface Mode
Start bit
(Z)
Ds
Ds
Figure 12.23 Direct Convention (SDIR = SINV = O/E = 0)
Ds
A
D0
D0
D0
Dp: Parity bit
DE: Error signal
Z
D1
D1
D1
Z
Output from the transmitting station
Output from the transmitting station
D2
D2
D2
A
D3
D3
D3
Z
D4
Z
D4
D4
D5
Z
D5
D5
D6
A
D6
D6
D7
A
Dp
D7
D7
Z
Dp
Dp
(Z) state
Output from
the receiving station
DE

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