R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 350

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 16-Bit Timer Pulse Unit (TPU)
(2)
Figure 9.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been
set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the
TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
Figure 9.20 illustrates the operation when counting upon TCNT_2 overflow/underflow has been
set for TCNT_1, and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
Rev. 3.00 Mar. 14, 2006 Page 312 of 804
REJ09B0104-0300
Examples of Cascaded Operation
TCNT_1
clock
TCNT_1
TCNT_2
clock
TCNT_2
TIOCA1,
TIOCA2
TGRA_1
TGRA_2
TCLKC
TCLKD
TCNT_2
TCNT_1
H'FFFF
H'03A1
FFFD
Figure 9.19 Example of Cascaded Operation (1)
Figure 9.20 Example of Cascaded Operation (2)
0000
FFFE
FFFF
0000
H'0000
0001
H'03A2
H'03A2
H'0000
0001
0002
0001
0000
H'0001
FFFF
0000