R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 510

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Controller Area Network (HCAN)
Rev. 3.00 Mar. 14, 2006 Page 472 of 804
REJ09B0104-0300
Bit
10
9
8
7 to 5
4
3, 2
1
0
Bit Name
IMR2
IMR1


IMR12

IMR9
IMR8
Initial
Value
1
1
0
All 1
1
All 1
1
1
R/W
R/W
R/W
R
R
R/W
R
R/W
R/W
Description
Remote Frame Request Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR2 (OVR0) is enabled. When set to 1, it is
masked.
Receive Message Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR1 (RM1) is enabled. When set to 1, it is
masked.
Reserved
This is a read-only bit and cannot be modified.
Reserved
These are read-only bits and cannot be modified.
Bus Operation Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR12 (OVR0) is enabled. When set to 1, it is
masked.
Reserved
These are read-only bits and cannot be modified.
Unread Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR9 (OVR0) is enabled. When set to 1, it is
masked.
Mailbox Empty Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR8 (SLE0) is enabled. When set to 1, it is
masked.