R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 251

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

8.1.3
PORT is an 8-bit read-only register that reflects the port pin status. A write to PORT is invalid.
When PORT is read, the DR bits that correspond to the respective DDR bits set to 1 are read and
the status of each pin whose corresponding DDR bit is cleared to 0 is also read regardless of the
ICR value.
The initial value of PORT is undefined and is determined based on the port pin status.
8.1.4
ICR is an 8-bit readable/writable register that controls the port input buffers.
For bits in ICR set to 1, the input buffers of the corresponding pins are valid. For bits in ICR
cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed
high.
When the pin functions as an input for the peripheral modules, the corresponding bits should be
set to 1. The initial value should be written to a bit whose corresponding pin is not used as an input
or is used as an analog input/output pin.
When PORT is read, the pin status is always read regardless of the ICR value. On-chip modules
are not affected by the pin status when the ICR value is cleared to 0.
If ICR is modified, an internal edge may occur depending on the pin status. Accordingly, ICR
should be modified when the corresponding input pins are not used. For example, in IRQ input,
modify ICR while the corresponding interrupt is disabled, clear the IRQF flag in ISR of the
interrupt controller to 0, and then enable the corresponding interrupt. If an edge occurs after the
ICR setting, the edge should be cancelled.
The initial value of ICR is H'00.
Bit
Bit Name
Initial Value
R/W
Note: The lower four bits are valid and the upper four bits are reserved for port 2 register (PORT2).
The lower seven bits are valid and the upper one bit is reserved for port 6 register (PORT6).
The upper seven bits are valid and the lower one bit is reserved for port A register (PORTA).
Port Register (PORTn) (n = 1 to 6, A, D, H, J, and K)
Input Buffer Control Register (PnICR) (n = 1 to 6, A, D, H, J, and K)
Undefined
Pn7
R
7
Undefined
Pn6
R
6
Undefined
Pn5
R
5
Undefined
Pn4
R
4
Undefined
Pn3
R
3
Rev. 3.00 Mar. 14, 2006 Page 213 of 804
Undefined
Pn2
R
2
Undefined
Pn1
R
1
Section 8 I/O Ports
REJ09B0104-0300
Undefined
Pn0
R
0