R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 68

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
2.5.2
PC is a 32-bit counter that indicates the address of the next instruction the CPU will execute. The
length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant
bit is ignored. (When the instruction code is fetched, the least significant bit is regarded as 0.
2.5.3
CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask
(I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C)
flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branch conditions for conditional branch (Bcc)
instructions.
Rev. 3.00 Mar. 14, 2006 Page 30 of 804
REJ09B0104-0300
Bit
7
6
Bit Name
I
UI
Program Counter (PC)
Condition-Code Register (CCR)
Initial
Value
1
Undefined R/W
SP (ER7)
R/W
R/W
Figure 2.11 Stack
Description
Interrupt Mask Bit
Masks interrupts when set to 1. This bit is set to 1 at the
start of an exception handling.
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions. This
bit can also be used as an interrupt mask bit.
User Bit or Interrupt Mask Bit
Stack area
Free area