R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 509

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13.3.13 Interrupt Mask Register (IMR)
IMR enables or disables interrupt requests by IRR interrupt flags. The reset interrupt flag cannot
be masked.
Bit
15
14
13
12
11
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
IMR7
IMR6
IMR5
IMR4
IMR3
IMR7
R/W
15
—
R
1
7
1
Initial
Value
1
1
1
1
1
IMR6
R/W
14
—
R
1
6
1
IMR5
R/W
13
—
R/W
R/W
R/W
R/W
R/W
R/W
R
1
5
1
IMR12
IMR4
Description
When this bit is cleared to 0, an interrupt request
by IRR7 (OVR0) is enabled. When set to 1, it is
masked.
When this bit is cleared to 0, an interrupt request
by IRR6 (ERS0) is enabled. When set to 1, it is
masked.
When this bit is cleared to 0, an interrupt request
by IRR5 (ERS0) is enabled. When set to 1, it is
masked.
When this bit is cleared to 0, an interrupt request
by IRR4 (OVR0) is enabled. When set to 1, it is
masked.
When this bit is cleared to 0, an interrupt request
by IRR3 (OVR0) is enabled. When set to 1, it is
masked.
Overload Frame Interrupt Mask
Bus Off Interrupt Mask
Error Passive Interrupt Mask
Receive Overload Warning Interrupt Mask
Transmit Overload Warning Interrupt Mask
R/W
R/W
12
1
4
1
IMR3
R/W
Section 13 Controller Area Network (HCAN)
11
—
R
1
3
1
Rev. 3.00 Mar. 14, 2006 Page 471 of 804
IMR2
R/W
10
—
R
1
2
1
IMR1
IMR9
R/W
R/W
9
1
1
1
REJ09B0104-0300
IMR8
R/W
—
R
8
0
0
1