R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 719

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
19.7
19.7.1
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby
mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop.
However, the contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip
peripheral functions other than the SCI, HCAN, and SSU, and the states of the I/O ports, are
retained. In this mode the oscillator stops, allowing power consumption to be significantly
reduced.
If the WDT is used as a watchdog timer, it is impossible to make a transition to software standby
mode. The WDT should be stopped before the SLEEP instruction execution.
19.7.2
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ14*), or
by means of the RES pin.
1. Clearing by interrupt
2. Clearing by RES pin
When an NMI or IRQ0 to IRQ14* interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS4 to STS0 in SBYCR, stable clocks are supplied to
the entire LSI, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ14* interrupt, set the
corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts
IRQ0 to IRQ11* is generated. Software standby mode cannot be cleared if the interrupt has
been masked on the CPU side or has been designated as a DMAC activation source.
Note: * By setting the SSIn bit in SSIER to 1, IRQ0 to IRQ14 can be used as a software
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low
until clock oscillation settles. When the RES pin goes high, the CPU begins reset exception
handling.
Software Standby Mode
Transition to Software Standby Mode
Clearing Software Standby Mode
standby mode clearing source.
Rev. 3.00 Mar. 14, 2006 Page 681 of 804
Section 19 Power-Down Modes
REJ09B0104-0300

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