R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 158

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Interrupt Controller
5.7
CPU Priority Control Function Over DMAC
The interrupt controller has a function to control the priority among the DMAC and the CPU by
assigning priority levels to the DMAC and CPU. Since the priority level can automatically be
assigned to the CPU on an interrupt occurrence, it is possible to execute the CPU interrupt
exception handling prior to the DMAC transfer.
The priority level of the CPU is assigned by bits CPUP2 to CPUP0 in CPUPCR. The priority level
of the DMAC is assigned to each channel by bits DMAP2 to DMAP0 in the DMA mode control
registers 0 to 3 (DMDR_0 to DMDR_3).
The priority control function over the DMAC is enabled by setting the CPUPCE bit in CPUPCR
to 1. When the CPUPCE bit is 1, the DMAC activation source is controlled according to the
respective priority level.
The priority level of the DMAC can be specified for each channel. The DMAC activation source
is controlled according to the priority level of the CPU and the priority level of the DMAC
indicated by bits DMAP2 to DMAP0. If the CPU has priority, the DMAC activation source is
held. The DMAC is activated when the condition by which the activation source is held is
cancelled (CPUCPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DMAP2
to DMAP0). When the different priority levels of the DMAC are assigned for the channels, the
channel having higher priority continues to transfer while the channel having lower priority than
the CPU is held.
There are two methods for assigning the priority level to the CPU by the IPSETE bit in CPUPCR.
Setting the IPSETE bit to 1 enables a function to automatically assign the value of the interrupt
mask bit of the CPU to the CPU priority level. Clearing the IPSETE bit to 0 disables the function
to automatically assign the priority level. Therefore, the priority level is assigned directly by
software rewriting bits CPUP2 to CPUP0. Even if the IPSETE bit is 1, the priority level of the
CPU is software assignable by rewriting the interrupt mask bit of the CPU (I bit in CCR or I2 to I0
bits in EXR).
The priority level which is automatically assigned when the IPSETE bit is 1 differs according to
the interrupt control mode.
In interrupt control mode 0, the I bit in CCR of the CPU is reflected in bit CPUP2. Bits CPUP1
and CPUP0 are fixed 0. In interrupt control mode 2, the values of bits I2 to I0 in EXR of the CPU
are reflected in bits CPUP2 to CPUP0.
Table 5.7 shows the CPU priority control.
Rev. 3.00 Mar. 14, 2006 Page 120 of 804
REJ09B0104-0300