R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 231

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(3)
Figure 7.35 shows an example of single address mode activated by the DREQ signal falling edge.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If
a high level of the DREQ signal has been detected until completion of the single cycle, receiving
the next transfer request resumes and then a low level of the DREQ signal is detected. This
operation is repeated until the transfer is completed.
B
DREQ
Address bus
DACK
DMA
operation
Channel
[1]
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the B signal is started to detect a high level of the
[4][7] When a high level of the DREQ signal has been detected, transfer enable is resumed after completion of the write cycle.
Activation Timing by DREQ Falling Edge
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer
request is held.
DREQ signal.
(A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].)
Figure 7.35 Example of Transfer in Single Address Mode Activated
Wait
[1]
Request
Min. of 3 cycles
released
[2]
Bus
Duration of transfer
request disabled
by DREQ Falling Edge
Single
[3]
Transfer destination
Transfer source/
DMA single
cycle
Wait
Transfer request
enable resumed
[4]
Request
Min. of 3 cycles
[5]
released
Rev. 3.00 Mar. 14, 2006 Page 193 of 804
Bus
Section 7 DMA Controller (DMAC)
Duration of transfer
request disabled
Single
[6]
Transfer destination
Transfer source/
DMA single
cycle
Wait
Transfer request
enable resumed
REJ09B0104-0300
[7]
released
Bus