R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 161

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.8.2
Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and
XORC. After any of these instructions is executed, all interrupts including NMI are disabled and
the next instruction is always executed. When the I bit is set by one of these instructions, the new
value becomes valid two states after execution of the instruction ends.
5.8.3
There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction, and for a period of
writing to the registers of the interrupt controller.
5.8.4
Interrupt operation differs between the EEPMOV.B and the EEPMOV.W instructions.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the transfer is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at the end of the individual transfer cycle. The PC value saved on the
stack in this case is the address of the next instruction. Therefore, if an interrupt is generated
during execution of an EEPMOV.W instruction, the following coding should be used.
5.8.5
With the MOVMD and MOVSD instructions, if an interrupt request is issued during the transfer,
interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved
on the stack in this case is the address of the MOVMD or MOVSD instruction. The transfer of the
remaining data is resumed after returning from the interrupt handling routine.
L1:
Instructions that Disable Interrupts
Times when Interrupts are Disabled
Interrupts during Execution of EEPMOV Instruction
Interrupts during Execution of MOVMD and MOVSD Instructions
EEPMOV.W
MOV.W R4,R4
BNE
L1
Rev. 3.00 Mar. 14, 2006 Page 123 of 804
Section 5 Interrupt Controller
REJ09B0104-0300