R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 491

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13.3.1
MCR controls the HCAN.
Bit
7
6
5
4, 3
2
1
Bit
Bit Name
Initial Value
R/W
Master Control Register (MCR)
Bit Name
MCR7

MCR5

MCR2
MCR1
MCR7
R/W
7
0
Initial
Value
0
0
0
All 0
0
0
—
R
6
0
MCR5
R/W
R/W
R/W
R
R/W
R
R/W
R/W
5
0
Description
HCAN Sleep Mode Release
When this bit is set to 1, the HCAN automatically
exits HCAN sleep mode on detection of CAN bus
operation.
This is a read-only bit and cannot be modified.
HCAN Sleep Mode
When this bit is set to 1, the HCAN enters HCAN
sleep mode. When this bit is cleared to 0, HCAN
sleep mode is released.
These are read-only bits and cannot be modified.
0: Transmission order determined by message
1: Transmission order determined by mailbox
When this bit is set to 1, the HCAN enters HCAN
HALT mode. When this bit is cleared to 0, HCAN
HALT mode is released.
Reserved
Reserved
Message Transmission Method
Halt Request
—
R
4
0
identifier priority
(buffer) number priority (TXPR1 > TXPR15)
Section 13 Controller Area Network (HCAN)
—
R
3
0
Rev. 3.00 Mar. 14, 2006 Page 453 of 804
MCR2
R/W
2
0
MCR1
R/W
1
0
REJ09B0104-0300
MCR0
R/W
0
1