R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 28

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 12.27 TEND Flag Set Timing during Transmission........................................................ 435
Figure 12.28 Sample Transmission Flowchart ........................................................................... 436
Figure 12.29 Data Re-Transfer Operation in SCI Reception Mode............................................ 437
Figure 12.30 Sample Reception Flowchart................................................................................. 438
Figure 12.31 Clock Output Fixing Timing ................................................................................. 438
Figure 12.32 Clock Stop and Restart Procedure......................................................................... 439
Figure 12.33 Sample Transmission using DMAC in Clocked Synchronous Mode.................... 443
Figure 12.34 Sample Flowchart for Mode Transition during Transmission............................... 445
Figure 12.35 Port Pin States during Mode Transition
Figure 12.36 Port Pin States during Mode Transition
Figure 12.37 Sample Flowchart for Mode Transition during Reception .................................... 447
Section 13 Controller Area Network (HCAN)
Figure 13.1 HCAN Block Diagram ............................................................................................ 450
Figure 13.2 Message Control Register Configuration ................................................................ 478
Figure 13.3 Standard Format ...................................................................................................... 478
Figure 13.4 Extended Format ..................................................................................................... 478
Figure 13.5 Message Data Configuration ................................................................................... 481
Figure 13.6 Hardware Reset Flowchart ...................................................................................... 485
Figure 13.7 Software Reset Flowchart ....................................................................................... 486
Figure 13.8 Detailed Description of One Bit .............................................................................. 487
Figure 13.9 Transmission Flowchart .......................................................................................... 490
Figure 13.10 Transmit Message Cancellation Flowchart ........................................................... 493
Figure 13.11 Reception Flowchart ............................................................................................. 494
Figure 13.12 Unread Message Overwrite Flowchart.................................................................. 497
Figure 13.13 HCAN Sleep Mode Flowchart .............................................................................. 498
Figure 13.14 HCAN Halt Mode Flowchart ................................................................................ 500
Figure 13.15 DMAC Transfer Flowchart ................................................................................... 502
Figure 13.16 High-Speed Interface Using PCA82C250............................................................. 503
Section 14 Synchronous Serial Communication Unit (SSU)
Figure 14.1 Block Diagram of SSU............................................................................................ 510
Figure 14.2 Relationship of Clock Phase, Polarity, and Data..................................................... 526
Figure 14.3 Relationship between Data Input/Output Pins and the Shift Register ..................... 527
Figure 14.4 Example of Initial Settings in SSU Mode ............................................................... 530
Figure 14.5 Example of Transmission Operation (SSU Mode).................................................. 532
Figure 14.6 Flowchart Example of Data Transmission (SSU Mode) ......................................... 533
Figure 14.7 Example of Reception Operation (SSU Mode) ....................................................... 535
Figure 14.8 Flowchart Example of Data Reception (SSU Mode) .............................................. 536
Figure 14.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode).......... 537
Figure 14.10 Conflict Error Detection Timing (Before Transfer) .............................................. 538
Figure 14.11 Conflict Error Detection Timing (After Transfer End) ......................................... 538
Rev. 3.00 Mar. 14, 2006 Page xxviii of xxxviii
(Internal Clock, Asynchronous Transmission) ..................................................... 446
(Internal Clock, Clocked Synchronous Transmission) ......................................... 446