R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 575

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

[3]
Figure 14.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)
[1]
[2]
No
Note: Hatching boxes represent SSU internal operations.
Data transferred from SSTDR to SSTRSR
TDRE set to 1 to start transmission
Clear TE and RE in SSER to 0
Write transmit data to SSTDR
Read receive data in SSRDR
TDRE automatically cleared
RDRF automatically cleared
End transmission/reception
Clear TEND in SSSR to 0
transmission/reception?
Read TDRE in SSSR
Has the 1 bit transfer
Read TEND in SSSR
Consecutive data
period elapsed?
Initial setting
Read SSSR
RDRF = 1?
ORER = 1?
TDRE = 1?
TEND = 1?
Yes
Start
Yes
No
Yes
Yes
No
Yes
No
No
No
Yes
Error processing
[4]
[5]
Section 14 Synchronous Serial Communication Unit (SSU)
[1] Initial setting:
[2] Check the SSU state and write transmit data:
[3] Check the SSU state:
[4] Receive error processing:
[5] Procedure for consecutive data transmission/reception:
Specify the transmit/receive data format.
Write transmit data to SSTDR after reading and
confirming that the TDRE bit in SSSR is 1. The TDRE
bit is automatically cleared to 0 and transmission/
reception is started by writing data to SSTDR.
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by RXI interrupt.
When a receive error occurs, execute the designated
error processing after reading the ORER bit in SSSR.
After that, clear the ORER bit to 0. While the ORER bit is
set to 1, transmission or reception is not resumed.
To continue serial data transmission/reception, confirm
that the TDRE bit is 1 meaning that SSTDR is ready to be
written to. After that, data can be written to SSTDR. The
TDRE bit is automatically cleared to 0 by writing data to
SSTDR.
Rev. 3.00 Mar. 14, 2006 Page 537 of 804
REJ09B0104-0300