R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 479

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.8.2
Table 12.13 shows the interrupt sources in smart card interface mode. A transmit end (TEI)
interrupt request cannot be used in this mode.
Table 12.13 SCI Interrupt Sources
Data transmission/reception using the DMAC is also possible in smart card interface mode,
similar to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are
simultaneously set to 1, thus generating a TXI interrupt. This activates the DMAC by a TXI
request thus allowing transfer of transmit data if the TXI request is specified as a source of DMAC
activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer
by the DMAC. If an error occurs, the SCI automatically re-transmits the same data. During re-
transmission, the TEND flag remains as 0, thus not activating the DMAC. Therefore, the SCI and
DMAC automatically transmit the specified number of bytes, including re-transmission in the case
of error occurrence. However, the ERS flag in SSR, which is set at error occurrence, is not
automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1
to enable an ERI interrupt request to be generated at error occurrence.
When transmitting/receiving data using the DMAC, be sure to set and enable the DMAC prior to
making SCI settings. For DMAC settings, see section 7, DMA Controller (DMAC).
In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This
activates the DMAC by an RXI request thus allowing transfer of receive data if the RXI request is
specified as a source of DMAC activation beforehand. The RDRF flag is automatically cleared to
0 at data transfer by the DMAC. If an error occurs, the RDRF flag is not set but the error flag is
set. Therefore, the DMAC is not activated and an ERI interrupt request is issued to the CPU
instead; the error flag must be cleared.
Name
ERI
RXI
TXI
Interrupts in Smart Card Interface Mode
Receive data full
Transmit data empty
Interrupt Source
Receive error or error
signal detection
Interrupt Flag
ORER, PER, or ERS
RDRF
TDRE
Section 12 Serial Communication Interface (SCI)
Rev. 3.00 Mar. 14, 2006 Page 441 of 804
DMAC Activation
Not possible
Possible
Possible
REJ09B0104-0300
Priority
High
Low