R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 91

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

2.7.3
The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op field), a register field (r field), an effective address extension (EA field), and a
condition field (cc).
Figure 2.14 shows examples of instruction formats.
• Operation Field
• Register Field
• Effective Address Extension
• Condition Field
Indicates the function of the instruction, and specifies the addressing mode and operation to be
carried out on the operand. The operation field always includes the first four bits of the
instruction. Some instructions have two operation fields.
Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or
4 bits. Some instructions have two register fields. Some have no register field.
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
Specifies the branch condition of Bcc instructions.
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
Basic Instruction Formats
op
op
op
Figure 2.14 Instruction Formats
cc
EA (disp)
op
rn
rn
EA (disp)
rm
rm
Rev. 3.00 Mar. 14, 2006 Page 53 of 804
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm, etc.
BRA d:16, etc
REJ09B0104-0300
Section 2 CPU