R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 183

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
30
29
28
27
26
25, 24
23
22 to 20 
Bit Name
DACKE
TENDE

DREQS
NRD

ACT
Initial
Value
0
0
0
0
0
All 0
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Description
DACK Signal Output Enable
Enables/disables the DACK signal output in single
address mode. This bit is ignored in dual address mode.
0: Enables DACK signal output
1: Disables DACK signal output
TEND Signal Output Enable
Enables/disables the TEND signal output.
0: Enables TEND signal output
1: Disables TEND signal output
Reserved
This bit is always read as 0. The write value should
always be 0.
DREQ Select
Selects whether a low level or the falling edge of the
DREQ signal used in external request mode is detected.
When a block transfer is performed in external request
mode, clear this bit to 0 to select the low level detection.
0: Low level detection
1: Falling edge detection (the first transfer after a
Next Request Delay
Selects the accepting timing of the next transfer request.
0: Starts accepting the next transfer request after
1: Starts accepting the next transfer request one cycle
Reserved
These are read-only bits and cannot be modified.
Active State
Indicates the operating state for the channel.
0: Waiting for a transfer request or a transfer disabled
1: Active state
Reserved
These are read-only bits and cannot be modified.
transfer enabled is detected on a low level)
completion of the current transfer
after completion of the current transfer
state by clearing the DTE bit to 0
Rev. 3.00 Mar. 14, 2006 Page 145 of 804
Section 7 DMA Controller (DMAC)
REJ09B0104-0300