R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 594

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 15 A/D Converter
15.4
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. When changing the operating mode or analog input
channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D
conversion. The ADST bit can be set to 1 at the same time as the operating mode or analog input
channel is changed.
15.4.1
In single mode, A/D conversion is to be performed only once on the analog input of the specified
single channel.
1. A/D conversion for the selected channel is started when the ADST bit in ADCSR is set to 1 by
2. When A/D conversion is completed, the A/D conversion result is transferred to the
3. When A/D conversion is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set
4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when
Rev. 3.00 Mar. 14, 2006 Page 556 of 804
REJ09B0104-0300
software or an external trigger input.
corresponding A/D data register of the channel.
to 1 at this time, an ADI interrupt request is generated.
A/D conversion ends. The A/D converter enters wait state. If the ADST bit is cleared to 0
during A/D conversion, A/D conversion stops and the A/D converter enters wait state.
Operation
Single Mode

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