R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 170

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller (BSC)
• Transfer data read or write by memory transfer instructions, block transfer instructions, or TAS
• From the target read to write in the bit manipulation instructions or memory operation
(2)
The DMAC sends the internal bus arbiter a request for the bus when an activation request is
generated.
Once the DMAC takes control of the bus, it continues the transfer processing cycles, or releases
the bus every transfer cycle.
The bus cannot be transferred in the following cases.
• Between a read cycle and the corresponding write cycle in dual address mode
While the IBCCS bit in BCR2 is cleared to 0, the bus cannot be transferred in the following cases.
• During 1-block data transfer in block transfer mode
• During burst access transfer
The DMAC releases the bus when the consecutive transfer cycles completed except the above
cycles.
6.8
In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.
6.9
All-Module-Clock-Stop Mode: In this LSI, if the ACSE bit in MSTPCR is set to 1 with the
setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFFFFFF), a transition is
made to the all-module-clock-stop mode. For details, see section 19, Power-Down Modes.
Rev. 3.00 Mar. 14, 2006 Page 132 of 804
REJ09B0104-0300
instruction.
(In the block transfer instructions, the bus can be transferred in the write cycle and the
following transfer data read cycle.)
instructions.
(In an instruction that performs no write operation according to the instruction condition, up to
a cycle corresponding the write cycle)
DMAC
Bus Controller Operation in Reset
Usage Notes