R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 124

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 4 Exception Handling
4.9
When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed by a word transfer instruction or a longword transfer instruction,
and the value of the stack pointer (SP: ER7) should always be kept even. Use the following
instructions to save registers:
• PUSH.W Rn (or MOV.W Rn, @-SP)
• PUSH.L ERn (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
• POP.W Rn (or MOV.W @SP+, Rn)
• POP.L ERn (or MOV.L @SP+, ERn)
Performing stack manipulation while SP is set to an odd value leads to an address error. Figure 4.3
shows an example of operation when the SP value is odd.
Rev. 3.00 Mar. 14, 2006 Page 86 of 804
REJ09B0104-0300
SP
[Legend]
CCR :
PC :
R1L :
SP :
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Usage Note
SP set to H'FFFEFF
Condition code register
Program counter
General register R1L
Stack pointer
TRAPA instruction executed
Figure 4.3 Operation when SP Value Is Odd
(Address error occurred)
SP
Data saved above SP
CCR
PC
MOV.B R1L, @-ER7 executed
SP
Contents of CCR lost
R1L
PC
H'FFFEFA
H'FFFEFB
H'FFFEFC
H'FFFEFD
H'FFFEFE
H'FFFEFF
Address