R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 826

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Rev. 3.00 Mar. 14, 2006 Page 788 of 804
REJ09B0104-0300
Item
Figure 14.9 Flowchart Example of
Simultaneous
Transmission/Reception (SSU
Mode)
14.4.7 Clock Synchronous
Communication Mode
Figure 14.12 Example of Initial
Settings in Clock Synchronous
Communication Mode
Figure 14.14 Flowchart Example
of Transmission Operation
Page Revision (See Manual for Details)
537
539
541
Amended
Amended
Deleted
[1]
[2]
[4]
[5]
[1]
[2]
Transmission/reception started
Clear TE and RE in SSER to 0
End transmission/reception
Clear TEND in SSSR to 0
transmission/reception?
Read TDRE in SSSR
Has the 1 bit transfer
Read TEND in SSSR
Specify TE, RE, TEIE, TIE, RIE, and
Specify SDOS, SSCKOS, SCSOS,
Specify CPOS, CKS2, CKS1, and
CEIE bits in SSER simultaneously
TE = 1 (transmission enabled)
Consecutive data
(TE = 1, RE = 1)
period elapsed?
Initial setting
TEND = 1?
TENDSTS, SCSATS, and
Start setting initial values
SSODTS bits in SSCR2
Read TDRE in SSSR
Start
CKS0 bits in SSMR
Yes
Yes
Initial setting
Start
End
No
No
No
Error processing

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