R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 235

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(4)
When an overflow on the extended repeat area occurs while the extended repeat area is specified
and the SARIE or DARIE bit in DACR is set to 1, an interrupt by an extended repeat area
overflow is requested. When the interrupt is requested, the DMA transfer is terminated, the DTE
bit in DMDR is cleared to 0, and the ESIF bit in DMDR is set to 1.
In dual address mode, even if an interrupt by an extended repeat area overflow occurs during a
read cycle, the following write cycle is performed.
In block transfer mode, even if an interrupt by an extended repeat area overflow occurs during a 1-
block transfer, the remaining data is transferred. The transfer is not terminated by an extended
repeat area overflow interrupt unless the current transfer is complete.
(5)
When the DTE bit in DMDR is cleared to 0 by the CPU, a transfer is completed after the current
DMA cycle and a DMA cycle in which the transfer request is accepted are completed.
In block transfer mode, a DMA transfer is completed after 1-block data is transferred.
(6)
When an NMI interrupt is requested, the DTE bits for all the channels are cleared to 0 and the
ERRF bit in DMDR_0 is set to 1. When an NMI interrupt is requested during a DMA transfer, the
transfer is forced to stop. To perform DMA transfer after an NMI interrupt is requested, clear the
ERRF bit to 0 and then set the DTE bits for the channels to 1.
The transfer end timings after an NMI interrupt is requested are shown below.
(a)
In dual address mode, a DMA transfer is completed after completion of the write cycle for one
transfer unit.
In single address mode, a DMA transfer is completed after completion of the bus cycle for one
transfer unit.
(b) Block Transfer Mode
A DMA transfer is forced to stop. Since a 1-block size of transfers is not completed, operation is
not guaranteed.
In dual address mode, the write cycle corresponding to the read cycle is performed. This is similar
to (a) in normal transfer mode.
Transfer End by Interrupt on Extended Repeat Area Overflow
Transfer End by Clearing DTE Bit in DMDR
Transfer End by NMI Interrupt
Normal Transfer Mode and Repeat Transfer Mode
Rev. 3.00 Mar. 14, 2006 Page 197 of 804
Section 7 DMA Controller (DMAC)
REJ09B0104-0300