R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 380

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.11
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 9.54 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
9.9.12
If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write
cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.
Figure 9.55 shows the operation timing when there is conflict between TCNT write and overflow.
Rev. 3.00 Mar. 14, 2006 Page 342 of 804
REJ09B0104-0300
Conflict between Overflow/Underflow and Counter Clearing
Conflict between TCNT Write and Overflow/Underflow
Figure 9.54 Conflict between Overflow and Counter Clearing
P
TCNT input
clock
TCNT
Counter clear
signal
TGF flag
TCFV flag
Figure 9.55 Conflict between TCNT Write and Overflow
P
Address
Write
TCNT
TCFV flag
H'FFFF
Disabled
H'FFFF
TGR write cycle
T1
TCNT address
T2
H'0000
M
TCNT write data