R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 535

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(4)
If the receive message identifier matches the mailbox identifier, the receive message is stored in
the mailbox regardless of whether the mailbox contains an unread message or not. If a message
overwrite occurs, the corresponding bit (UMSR0 to UMSR15) in the unread message register
(UMSR) is set. In overwriting an unread message, the unread message register (UMSR) is set
when a new message is received before the corresponding bit in the receive complete register
(RXPR) has been cleared. If the unread interrupt flag (IRR9) in the interrupt mask register (IMR)
is set to enable interrupts at this time, an interrupt can be sent to the CPU. Figure 13.12 shows a
flowchart for unread message overwriting.
Unread message overwrite
Message control/message data read
Figure 13.12 Unread Message Overwrite Flowchart
Unread message overwrite
Interrupt to CPU
Clear IRR9
UMSR = 1
IMR9 = 1?
IRR9 = 1
End
No
Yes
Section 13 Controller Area Network (HCAN)
Rev. 3.00 Mar. 14, 2006 Page 497 of 804
: Settings by user
: Processing by hardware
REJ09B0104-0300