R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 27

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Watchdog Timer (WDT)
Figure 11.1 Block Diagram of WDT .......................................................................................... 367
Figure 11.2 Operation in Watchdog Timer Mode....................................................................... 372
Figure 11.3 Operation in Interval Timer Mode........................................................................... 373
Figure 11.4 Writing to TCNT, TCSR, and RSTCSR.................................................................. 374
Figure 11.5 Conflict between TCNT Write and Increment ........................................................ 375
Section 12 Serial Communication Interface (SCI)
Figure 12.1 Block Diagram of SCI............................................................................................. 378
Figure 12.2 Data Format in Asynchronous Communication
Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 407
Figure 12.4 Phase Relation between Output Clock and Transmit Data
Figure 12.5 Sample SCI Initialization Flowchart ....................................................................... 409
Figure 12.6 Example of Operation for Transmission in Asynchronous Mode
Figure 12.7 Sample Serial Transmission Flowchart ................................................................... 411
Figure 12.8 Example of SCI Operation for Reception
Figure 12.9 Sample Serial Reception Flowchart (1)................................................................... 414
Figure 12.9 Sample Serial Reception Flowchart (2)................................................................... 415
Figure 12.10 Example of Communication Using Multiprocessor Format
Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 418
Figure 12.12 Example of SCI Operation for Reception
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 420
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 421
Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First)..................... 422
Figure 12.15 Sample SCI Initialization Flowchart ..................................................................... 423
Figure 12.16 Example of Operation for Transmission in Clocked Synchronous Mode ............. 425
Figure 12.17 Sample Serial Transmission Flowchart ................................................................. 425
Figure 12.18 Example of Operation for Reception in Clocked Synchronous Mode................... 426
Figure 12.19 Sample Serial Reception Flowchart ...................................................................... 427
Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 428
Figure 12.21 Pin Connection for Smart Card Interface .............................................................. 429
Figure 12.22 Data Formats in Normal Smart Card Interface Mode............................................ 430
Figure 12.23 Direct Convention (SDIR = SINV = O/E = 0) ...................................................... 430
Figure 12.24 Inverse Convention (SDIR = SINV = O/E = 1)..................................................... 431
Figure 12.25 Receive Data Sampling Timing in Smart Card Interface Mode
Figure 12.26 Data Re-Transfer Operation in SCI Transmission Mode ...................................... 435
(Example with 8-Bit Data, Parity, Two Stop Bits) ................................................. 405
(Asynchronous Mode) ............................................................................................ 408
(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 410
(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 412
(Transmission of Data H'AA to Receiving Station A).......................................... 417
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................. 419
(When Clock Frequency is 372 Times the Bit Rate) ............................................ 432
Rev. 3.00 Mar. 14, 2006 Page xxvii of xxxviii