R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 223

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(2)
In burst mode, one byte, one word, or one longword of data continues to be transferred until the
transfer end condition is satisfied.
When a burst transfer starts, a transfer request from a channel having priority is suspended until
the burst transfer is completed.
In figure 7.27, the TEND signal output is enabled and data is transferred in words from the
external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer
mode by burst access.
B
Address
bus
RD
HHWR,
HLWR
LHWR,
LLWR
TEND
Normal Transfer Mode (Burst Mode)
Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access
Bus
released
High
read cycle
DMA
write cycle
DMA
read cycle
DMA
Burst transfer
write cycle
DMA
Rev. 3.00 Mar. 14, 2006 Page 185 of 804
Section 7 DMA Controller (DMAC)
read cycle
DMA
Last transfer cycle
write cycle
DMA
REJ09B0104-0300
Bus
released