R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 591

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

15.3.2
ADCSR controls A/D conversion operations.
Bit
7
6
5
4
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written to this bit, to clear the flag.
Bit Name
ADF
ADIE
ADST

A/D Control/Status Register (ADCSR)
R/(W)*
ADF
7
0
Initial
Value
0
0
0
0
ADIE
R/W
6
0
R/W
R/(W)* A/D End Flag
R/W
R/W
R
ADST
R/W
5
0
Description
A status flag that indicates the end of A/D conversion.
[Setting conditions]
•
•
[Clearing conditions]
•
•
A/D Interrupt Enable
When this bit is set to 1, ADI interrupts by ADF are
enabled.
A/D Start
Clearing this bit to 0 stops A/D conversion, and the A/D
converter enters wait state.
Setting this bit to 1 starts A/D conversion. In single mode,
this bit is cleared to 0 automatically when A/D conversion
on the specified channel ends. In scan mode, A/D
conversion continues sequentially on the specified
channels until this bit is cleared to 0 by software or a
reset.
Reserved
This is a read-only bit and cannot be modified.
When A/D conversion ends in single mode
When A/D conversion ends on all specified channels
in scan mode
When 0 is written after reading ADF = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
When the DMAC is activated by an ADI interrupt and
ADDR is read
—
R
4
0
CH3
R/W
3
0
Rev. 3.00 Mar. 14, 2006 Page 553 of 804
CH2
R/W
2
0
Section 15 A/D Converter
CH1
R/W
1
0
REJ09B0104-0300
CH0
R/W
0
0