R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 226

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
(5)
Figure 7.30 shows an example of normal transfer mode activated by the DREQ signal low level.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the write cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is
completed.
Rev. 3.00 Mar. 14, 2006 Page 188 of 804
REJ09B0104-0300
B
DREQ
Address bus
DMA
operation
Channel
[1]
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed after completion of the write cycle.
Activation Timing by DREQ Low Level
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer
request is held.
(A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].)
Wait
Figure 7.30 Example of Transfer in Normal Transfer Mode Activated
[1]
Request
Min. of 3 cycles
Bus released
[2]
Read
[3]
Duration of transfer
request disabled
DMA read
Transfer
source
cycle
Write
by DREQ Low Level
Transfer request enable resumed
DMA write
destination
Transfer
cycle
Wait
[4]
Request
Min. of 3 cycles
Bus released
[5]
Read
Duration of transfer
[6]
request disabled
DMA read
Transfer
cycle
source
Write
Transfer request enable resumed
DMA write
destination
Transfer
cycle
Wait
[7]
Bus released