R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 465

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.6.5
Figure 12.20 shows a sample flowchart for simultaneous serial transmit and receive operations.
After initializing the SCI, the following procedure should be used for simultaneous serial data
transmit and receive operations. To switch from transmit mode to simultaneous transmit and
receive mode, after checking that the SCI has finished transmission and the TDRE and TEND
flags are set to 1, clear the TE bit to 0. Then simultaneously set both the TE and RE bits to 1 with
a single instruction. To switch from receive mode to simultaneous transmit and receive mode,
after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking that
the RDRF bit and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set
both the TE and RE bits to 1 with a single instruction.
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous
Mode)
[3]
No
No
Read receive data in RDR and
clear RDRF flag in SSR to 0
Clear ORER flag in SSR to 0
Read ORER flag in SSR
Clear RE bit in SCR to 0
Read RDRF flag in SSR
Overrun error processing
Figure 12.19 Sample Serial Reception Flowchart
All data received
Error processing
Start reception
Initialization
ORER = 1
RDRF = 1
<End>
<End>
Yes
Yes
No
(Continued below)
Error processing
Yes
[2]
[1]
[3]
[4]
[5]
Section 12 Serial Communication Interface (SCI)
[1] SCI initialization:
[2] [3] Receive error processing:
[4] SCI state check and receive data
[5] Serial reception continuation
The RxD pin is automatically
designated as the receive data input
pin.
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Reception cannot be resumed if the
ORER flag is set to 1.
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0. Transition of the RDRF flag from
0 to 1 can also be identified by an RXI
interrupt.
procedure:
To continue serial reception, before
the MSB (bit 7) of the current frame is
received, reading the RDRF flag,
reading RDR, and clearing the RDRF
flag to 0 should be finished. However,
the RDRF flag is cleared automatically
when the DMAC is initiated by a
receive data full interrupt (RXI) and
reads data from RDR.
Rev. 3.00 Mar. 14, 2006 Page 427 of 804
REJ09B0104-0300