R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 229

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.4.11
(1)
In single address mode, one byte, one word, or one longword of data is transferred at a single
transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the
CPU are executed in the bus released cycles.
In figure 7.33, the TEND signal output is enabled and data is transferred in bytes from the external
8-bit 2-state access space to the external device in single address mode (read).
Single Address Mode (Read and Cycle Stealing)
Bus Cycles in Single Address Mode
Figure 7.33 Example of Transfer in Single Address Mode (Byte Read)
B
Address bus
RD
DACK
TEND
released
Bus
DMA read
cycle
released
Bus
DMA read
cycle
released
Bus
DMA read
cycle
Rev. 3.00 Mar. 14, 2006 Page 191 of 804
released
Bus
Section 7 DMA Controller (DMAC)
DMA read
Last transfer
cycle
cycle
released
Bus
REJ09B0104-0300