R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 375

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.9
9.9.1
Operation of the TPU can be disabled or enabled using the module stop control register. The initial
setting is for operation of the TPU to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 19, Power-Down Modes.
9.9.2
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a
narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9.46 shows the input clock
conditions in phase counting mode.
Figure 9.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
P
Address
Status flag
Interrupt request
signal
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Usage Notes
Module Stop Mode Setting
Input Clock Restrictions
Figure 9.45 Timing for Status Flag Clearing by DMAC Activation (2)
Note: Phase difference, Overlap
Period in which the next transfer request is masked
Pulse width
Overlap
Pulse width
difference
Phase
2.5 states
Overlap
difference
Source address
Phase
Pulse width
Period of interrupt request signal clearing
1.5 states
read cycle
Period of flag clearing
DMAC
Pulse width
Rev. 3.00 Mar. 14, 2006 Page 337 of 804
Section 9 16-Bit Timer Pulse Unit (TPU)
Destination address
write cycle
DMAC
Pulse width
REJ09B0104-0300