R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 472

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Serial Communication Interface (SCI)
12.7.6
Data transmission in smart card interface mode (except in block transfer mode) is different from
that in normal serial communication interface mode in that an error signal is sampled and data can
be re-transmitted. Figure 12.26 shows the data re-transfer operation during transmission.
1. If an error signal from the receiving end is sampled after one frame of data has been
2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is
3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1.
4. In this case, one frame of data is determined to have been transmitted including re-transfer, and
Figure 12.28 shows a sample flowchart for transmission. All the processing steps are
automatically performed using a TXI interrupt request to activate the DMAC. In transmission, the
TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request
if the TIE bit in SCR has been set to 1. This activates the DMAC by a TXI request thus allowing
transfer of transmit data if the TXI interrupt request is specified as a source of DMAC activation
beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the
DMAC. If an error occurs, the SCI automatically re-transmits the same data. During re-
transmission, TEND remains as 0, thus not activating the DMAC. Therefore, the SCI and DMAC
automatically transmit the specified number of bytes, including re-transmission in the case of error
occurrence. However, the ERS flag is not automatically cleared; the ERS flag must be cleared by
previously setting the RIE bit to 1 to enable an ERI interrupt request to be generated at error
occurrence.
When transmitting/receiving data using the DMAC, be sure to set and enable the DMAC prior to
making SCI settings. For DMAC settings, see section 7, DMA Controller (DMAC).
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transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the
RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled.
re-transferred from TDR to TSR allowing automatic data retransmission.
the TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in
SCR is set to 1. Writing transmit data to TDR starts transmission of the next data.
Data Transmission (Except in Block Transfer Mode)