R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 481

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.9.5
The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR irrespective of the TDRE flag status. However, if new data is written
to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR
yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the
TDRE flag is set to 1.
12.9.6
• When the external clock source is used as a synchronization clock, update TDR by the DMAC
• When using the DMAC to read RDR, be sure to set the receive end interrupt (RXI) as the
and wait for at least five Pφ clock cycles before allowing the transmit clock to be input. If the
transmit clock is input within four clock cycles after TDR modification, the SCI may
malfunction (figure 12.33).
DMAC activation source.
Figure 12.33 Sample Transmission using DMAC in Clocked Synchronous Mode
Relation between Writing to TDR and TDRE Flag
Restrictions on Using DMAC
SCK
TDRE
Serial data
Note: When external clock is supplied, t must be more than four clock cycles.
t
LSB
D0
D1
D2
D3
Section 12 Serial Communication Interface (SCI)
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Rev. 3.00 Mar. 14, 2006 Page 443 of 804
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REJ09B0104-0300