R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 638

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 17 Flash Memory (0.18-(m F-ZTAT Version)
(1)
The SCI_4 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data,
one stop bit, and no parity.
When a transition to boot mode is made, the boot program embedded in this LSI is initiated.
When the boot program is initiated, this LSI measures the low period of asynchronous serial
communication data (H'00) transmitted consecutively by the host, calculates the bit rate, and
adjusts the bit rate of the SCI_4 to match that of the host.
When bit rate adjustment is completed, this LSI transmits 1 byte of H'00 to the host as the bit
adjustment end sign. When the host receives this bit adjustment end sign normally, it transmits 1
byte of H'55 to this LSI. When reception is not executed normally, initiate boot mode again. The
bit rate may not be adjusted within the allowable range depending on the combination of the bit
rate of the host and the system clock frequency of this LSI. Therefore, the transfer bit rate of the
host and the system clock frequency of this LSI must be as shown in table 17.6.
Table 17.6 System Clock Frequency for Automatic-Bit-Rate Adjustment
Rev. 3.00 Mar. 14, 2006 Page 600 of 804
REJ09B0104-0300
Bit Rate of Host
9,600 bps
19,200 bps
Serial Interface Setting by Host
Start
bit
Figure 17.7 Automatic-Bit-Rate Adjustment Operation
System Clock Frequency of This LSI External Clock Frequency
8 to 18 MHz
16 to 18 MHz
D0
Measure low period (9 bits) (data is H'00)
D1
D2
D3
D4
D5
4 to 9 MHz
8 to 9 MHz
D6
D7
High period of
at least 1 bit
Stop bit