R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 530

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Controller Area Network (HCAN)
(6)
Message transmission cancellation
Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait
message. A transmit wait message is canceled by setting the bit for the corresponding mailbox
(TXCR1 to TXCR15) to 1 in the transmit cancel register (TXCR). Clearing the transmit wait
register (TXPR) does not cancel transmission. When cancellation is executed, the transmit wait
register (TXPR) is automatically reset, and the corresponding bit is set to 1 in the abort
acknowledge register (ABACK), and then an interrupt to the CPU can be requested. Also, if the
corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and
the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are both
simultaneously set to enable interrupts, interrupts may be sent to the CPU.
However, a transmit wait message cannot be canceled at the following times:
• During internal arbitration or CAN bus arbitration
• During data frame or remote frame transmission
Rev. 3.00 Mar. 14, 2006 Page 492 of 804
REJ09B0104-0300