R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 475

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.7.7
Data reception in smart card interface mode is similar to that in normal serial communication
interface mode. Figure 12.29 shows the data re-transfer operation during reception.
1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI
2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1.
3. If no parity error is detected, the PER bit in SSR is not set to 1.
4. In this case, data is determined to have been received successfully, and the RDRF bit in SSR is
Figure 12.30 shows a sample flowchart for reception. All the processing steps are automatically
performed using an RXI interrupt request to activate the DMAC. In reception, setting the RIE bit
to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1. This activates
the DMAC by an RXI request thus allowing transfer of receive data if the RXI interrupt request is
specified as a source of DMAC activation beforehand. The RDRF flag is automatically cleared to
0 at data transfer by the DMAC. If an error occurs during reception, i.e., either the ORER or PER
flag is set to 1, a transmit/receive error interrupt (ERI) request is generated and the error flag must
be cleared. If an error occurs, the DMAC is not activated and receive data is skipped, therefore,
the number of bytes of receive data specified in the DMAC is transferred. Even if a parity error
occurs and the PER bit is set to 1 in reception, receive data is transferred to RDR, thus allowing
the data to be read.
Note: For operations in block transfer mode, see section 12.4, Operation in Asynchronous Mode.
interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the
next parity bit is sampled.
set to 1. Here, an RXI interrupt request is generated if the RIE bit in SCR is set to 1.
RDRF
PER
Serial Data Reception (Except in Block Transfer Mode)
Ds
Figure 12.29 Data Re-Transfer Operation in SCI Reception Mode
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
nth transfer frame
[2]
[1]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Retransfer frame
Section 12 Serial Communication Interface (SCI)
Rev. 3.00 Mar. 14, 2006 Page 437 of 804
(DE)
[4]
[3]
Ds D0 D1 D2 D3 D4
transfer frame
REJ09B0104-0300
(n + 1) th