R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 539

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
13.5
Table 13.4 lists the HCAN interrupt sources. These sources can be masked except the reset
processing interrupt by power-on reset (IRR0). Masking is implemented using the mailbox
interrupt mask register (MBIMR), interrupt mask register (IMR), and IRQ enable register (IER).
For details on the interrupt vector of each interrupt source, refer to section 5, Interrupt Controller.
Table 13.4 HCAN Interrupt Sources
Name
ERS0/OVR0
RM0
RM1
SLE0
Interrupt Sources
Description
Error passive interrupt (TEC ≥ 128 or REC ≥ 128)
Bus off interrupt (TEC ≥ 256)
Reset processing interrupt by power-on reset
Remote frame reception
Error warning interrupt (TEC ≥ 96)
Error warning interrupt (REC ≥ 96)
Overload frame transmission interrupt
Unread message overwrite
Detection of CAN bus operation in HCAN sleep mode
Mailbox 0 message reception
Mailbox 1-15 message reception
Message transmission/cancellation
Section 13 Controller Area Network (HCAN)
Rev. 3.00 Mar. 14, 2006 Page 501 of 804
Interrupt
Flag
IRR5
IRR6
IRR0
IRR2
IRR3
IRR4
IRR7
IRR9
IRR12
IRR1
IRR1
IRR8
REJ09B0104-0300
DMAC
Activation
Not possible
Possible
Not possible
Not possible

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