R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 60

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
• Exception Vector Table and Memory Indirect Branch Addresses
• Stack Structure
Rev. 3.00 Mar. 14, 2006 Page 22 of 804
REJ09B0104-0300
In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The structure of the exception vector table is shown in
figure 2.2.
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception
handling are shown in figure 2.3. The PC contents are saved or restored in 16-bit units.
SP
Notes: 1.
(a) Subroutine Branch
2.
3.
Figure 2.2 Exception Vector Table (Normal Mode)
When EXR is not used it is not stored on the stack.
SP when EXR is not used.
Ignored on return.
H'0000
H'0001
H'0002
H'0003
Figure 2.3 Stack Structure (Normal Mode)
(16 bits)
PC
Reset exception vector
Reset exception vector
(SP
SP
*
2
)
(b) Exception Handling
Exception
vector table
Reserved*
(16 bits)
CCR*
EXR*
CCR
PC
1
3
1
,*
3