R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 576

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 14 Synchronous Serial Communication Unit (SSU)
14.4.6
When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is
cleared to 0, the SCS pin functions as an input (Hi-Z) to detect a conflict error. The detection
period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after transfer ends.
When a low level signal is input to the SCS pin within the period, a conflict error occurs. At this
time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0.
Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0
Rev. 3.00 Mar. 14, 2006 Page 538 of 804
REJ09B0104-0300
before resuming the transmission or reception.
External input to SCS
Internal-clocked SCS
MSS
Internal signal for
transfer enable
CE
SCS output
P
SCS
MSS
Internal signal for
transfer enable
CE
SCS Pin Control and Conflict Error
Figure 14.11 Conflict Error Detection Timing (After Transfer End)
Figure 14.10 Conflict Error Detection Timing (Before Transfer)
(Hi-Z)
Transfer
end
detection period
Conflict error
Data written
to SSTDR
internally clocking SCS
Worst time for
Conflict error detection period
(Hi-Z)